Japanese Patent Application Laid-Open Publication No. 2006-237385 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2007-213375 (Patent Document 2) describe a semiconductor device in which a plurality of memory chips and a data processing chip controlling the plurality of memory chips are mounted side by side on a wiring substrate.
Japanese Patent Application Laid-Open Publication No. H06-151639 (Patent Document 3) describes a semiconductor device in which a ground pin and a power supply pin of a plurality of pins (terminals) of the wiring substrate are continuously arranged in series from the inside to the outside.